Difference between <= and >= in VHDL? -

can please tell me difference between <= , >= in vhdl?i know greater than/less or equal sign.can precise , explain code of line how execution takes place.i know signal assignment use <= example in state machines or whenever use when >= pops out.can please tell me difference?

there difference writing these in if-statements , elsewhere.

when using these in if-statements mathematical operation taking place. wrote comparision done, checking if value great-or-equal, smaller-or-equal value compare to.

when writing codes outside of if-statements part of vhdl syntax , has no mathematical meaning, how languagre constructed.

signal_a <= signal_b -- assign signal b signal a

-- when whats inside when block case when => -- stuff when others => -- other stuff end case;